This invention relates to improvements an electrode-lead layer units included in a semiconductor device and more particularly to electrode-lead layer units included in a giant scale integrated circuit (abbreviated as "GSI circuit") contaning extremely fine lead layers and also electrode-lead layer units used with a metal oxide semiconductor field effect transistor (abbreviated as "MOS FET") through which a large amount of current flows.
The prior art MOS FET is constructed, for example, with such a cross section as shown in FIG. 1. Formed in an N-type or P-type semiconductor substrate 1 are a source region 2 and drain region 3 by diffusion of impurities with the opposite type of conductivity to the semiconductor substrate. A thin gate oxide layer 4 and field oxide layer 5 are provided, for example, by oxidation or gas phase growth. A conductive layer made of, for example, aluminium is laminated all over the above-mentioned deposited elements by evaporation or gas phase growth, followed by selective etching to provide a source electrode 6, gate electrode 7 and lead layer 8 etc. Mounted on said assembled mass is an insulating layer (not shown) prepared from, for example, silicate glass containing phosphorus or boron. The electrode-lead layer unit has a width of several or scores of microns and a thickness of several microns. The gate electrode 7 through which little current runs can be made narrower than the source electrode 6 and drain electrode (not shown). However, the electrode-lead layer unit has a substantially uniform thickness.
The electrode-lead layer unit should preferably be made narrow to integrate MOS FET's with high density or render an entire semiconductor device compact. Hitherto, however, considerable difficulties have been encountered in consideration of etching precision and current capacity in reducing the width of source and drain electrodes and lead layers connected thereto, where a relatively large amount of current is allowed to pass through these electrodes and lead layers. For instance, an attempt to make a lead layer narrow, particularly about as narrow as its thickness tends to cause the lead layer to be easily broken during crosswise etching. Conversely, an attempt to restrict the degree of etching for prevention of the breakage of the lead layer is likely to engender short-circuiting between adjacent lead layers. Further, if a lead layer is made thin to elevate etching precision, then the current capacity of the lead layer will decrease, and passage of excess current will lead to the breakage of the lead layer. Accordingly, it has been impossible to decrease not only the width of an input lead layer connected to a power source and output lead layer, but also that of source and drain electrodes, to a lower level than that which corresponds to an amount of current passing through these elements. The above-mentioned problems arise not only with a GSI circuit which contains circuit elements integrated with as high a density as tens of thousands per square millimeter and for which lead layers used are only allowed to have a width ranging from several microns to several thousand Angstrom units, but also with any other form of semiconductor device.
Where a lead layer is formed on a semiconductor substrate by evaporating, for example, an aluminium conductor, there has hitherto occurred the drawback that no thermal deposition takes place in an uneven boundary region on the surface of a substrate which results from formation of an oxide layer, namely, on the inner wall of an etched hole, possibly giving rise to the breakage of the lead layer. Even if thermal deposition of the lead layer does take place, part of the lead layer is likely to be removed by the subsequent etching with the resultant breakage, unless the lead layer has a uniform large thickness. Therefore, a customary practice to resolve the above-mentioned difficulty has been to cause the inner wall of the etched hole to be inclined upward at an angle of about 20.degree. to 25.degree. to a horizontal plane in order to attain full thermal deposition of the lead layer. Though a gentler inclination of the inner wall of the etched hole is less likely to cause the breakage of the lead layer, yet said inclination, regardless of the angle thereof, presents difficulties in integrating numerous circuit elements with an increased density or rendering an entire semiconductor device more compact.
A lead pad intended to be connected to an external lead terminal by means of, for example, a gold wire has hitherto been accompanied with the drawback of being readily broken by a mechanical force applied during said wire bonding, because said lead pad has an insufficient thickness.